p.6
Instruction Set Architecture (ISA)
What is a Register-Register (RISC) architecture?
An architecture that can access memory only via load and store instructions.
p.18
MIPS Architecture Overview
What is the maximum memory capacity of the MIPS 32 processor?
Up to 2^32 bytes, which equals 2^30 words.
p.4
Instruction Set Architecture (ISA)
What does Instruction Set Architecture (ISA) represent?
WHAT the computer does (logical view).
p.6
Instruction Set Architecture (ISA)
What are the two early types of instruction set architectures?
Accumulator-based and Stack-based.
p.24
Addressing Modes in Computer Architecture
What is Register Addressing in MIPS?
Where the operand is a register (R - Type).
p.24
Addressing Modes in Computer Architecture
What defines Immediate Addressing in MIPS?
Where the operand is a constant in the instruction (I - Type, ALU).
p.17
MIPS Architecture Overview
What is the primary feature of MIPS 32 Architecture?
It utilizes a RISC (Reduced Instruction Set Computer) design.
p.6
Instruction Set Architecture (ISA)
What is a Register-Memory (CISC) architecture?
An architecture that can access a memory location as part of any instruction.
p.7
General Purpose Registers and Memory Addressing
Why do general purpose registers dominate in computer architecture?
They provide flexibility and efficiency in data processing and instruction execution.
p.4
Computer Architecture Overview
What does Computer Organization represent?
HOW the ISA is implemented (physical view).
p.5
Instruction Set Architecture (ISA)
What are the components included in an ISA?
Instructions and Instruction Formats, Data Types, Encodings, and Representations, Programmable Storage, Addressing Modes, and Handling Exceptional Conditions.
p.6
Instruction Set Architecture (ISA)
What replaced accumulator and stack-based architectures?
General-Purpose Register (GPR) architectures.
p.14
Data Types and Operand Sizes
What are the possible operand sizes in the Intel 80386?
8, 16, 32, 48, 64, or 80 bits long.
p.6
Instruction Set Architecture (ISA)
What is a Memory-Memory architecture?
An architecture that can access two or three memory locations per instruction, not used today.
p.23
Instruction Encoding Techniques
What is included in the I-Type instruction format?
A 16-bit immediate constant.
p.30
General Purpose Registers and Memory Addressing
How do you convert the jump target in words to bytes?
Multiply the jump target by 4.
p.3
MIPS Architecture Overview
What does 'sw $16, 0($2)' accomplish?
Stores the word in register $16 into memory at the address in register $2 plus an offset of 0.
p.1
Cost of Software Development
What do improved technologies enable?
They make new applications possible.
p.5
Instruction Set Architecture (ISA)
What is one advantage of having an ISA?
Different implementations of the same architecture.
p.4
Computer Architecture Overview
What is Computer Architecture?
Computer Architecture = Instruction Set Architecture + Computer Organization.
p.17
MIPS Architecture Overview
What does MIPS stand for in MIPS 32 Architecture?
Microprocessor without Interlocked Pipelined Stages.
p.5
Instruction Set Architecture (ISA)
Why is an ISA easier to change than hardware?
Because it standardizes instructions and machine language bit patterns.
p.5
Instruction Set Architecture (ISA)
What is a disadvantage of an ISA?
It sometimes prevents using new innovations.
p.8
General Purpose Registers and Memory Addressing
What is the common definition of memory in most architectures?
Memory is defined as byte addressable.
p.2
Instruction Set Architecture (ISA)
What is the role of the Instruction Set Architecture (ISA)?
The ISA forms an abstraction layer that sets the requirements for both compiler and CPU designers.
p.1
Cost of Software Development
How does architecture influence software development?
It is continually changing.
p.22
General Purpose Registers and Memory Addressing
What is the purpose of the MIPS register file?
To store and manage the general-purpose registers used in MIPS architecture.
p.23
Instruction Encoding Techniques
What does the R-Type instruction format primarily involve?
Register-to-register instructions.
p.22
General Purpose Registers and Memory Addressing
How many general-purpose registers does the MIPS architecture have?
32 general-purpose registers.
p.6
Instruction Set Architecture (ISA)
What is a characteristic of Memory-Memory architecture?
It has a large variation in instruction size and work per instruction (CPI).
p.26
Instruction Encoding Techniques
What is the purpose of the 'rt' field in MIPS R-Type instructions?
It represents the second register source operand.
p.7
General Purpose Registers and Memory Addressing
What is the typical use of general purpose registers in a CPU?
To store temporary data and intermediate results during computations.
p.11
Instruction Set Architecture (ISA)
What are typical operations in computer architecture?
Basic actions performed by a computer, such as arithmetic, logic, control, and data transfer.
p.30
General Purpose Registers and Memory Addressing
What is the purpose of the jump target in MIPS J-Type instructions?
It specifies the jump memory address in words.
p.3
MIPS Architecture Overview
What does the instruction 'lw $15, 0($2)' do?
Loads a word from memory into register $15 from the address in register $2 plus an offset of 0.
p.11
Instruction Set Architecture (ISA)
What does a logic operation entail?
Operations that involve Boolean logic, such as AND, OR, NOT.
p.14
Instruction Encoding Techniques
What do the first bytes of an instruction generally contain?
Opcode, mode specifiers, and register fields.
p.3
Control Signals and Machine Interpretation
What is the function of the ALUOP control signal?
It determines the operation performed by the ALU based on the instruction.
p.8
General Purpose Registers and Memory Addressing
How is word size defined differently by architectures?
Word size can be 2 bytes (Intel x86), 4 bytes (MIPS), or larger.
p.3
Instruction Set Architecture (ISA)
What is the role of an assembler?
To convert assembly language programs into machine language.
p.12
Instruction Encoding Techniques
Which architectures use hybrid encoding?
Micro MIPS and ARM Thumb.
p.21
General Purpose Registers and Memory Addressing
What is the function of the $gp register?
It is the global pointer that points to global data.
p.16
Instruction Encoding Techniques
How does instruction encoding impact computer architecture?
It impacts size and ease of decoding.
p.25
Instruction Encoding Techniques
What does R-type instruction format represent?
It is used for register-based operations.
p.7
General Purpose Registers and Memory Addressing
What are general purpose registers?
Registers that can hold data, addresses, or instructions and are used for various operations in a CPU.
p.5
Instruction Set Architecture (ISA)
What does ISA stand for?
Instruction Set Architecture.
p.5
Instruction Set Architecture (ISA)
What is the purpose of an Instruction Set Architecture?
It serves as an abstract interface between hardware and the lowest-level software.
p.24
Addressing Modes in Computer Architecture
What is Base or Displacement Addressing?
Where the operand is at the memory location whose address is the sum of a register and a constant in the instruction (I - Type, load/store).
p.24
Addressing Modes in Computer Architecture
What is Pseudodirect Addressing in MIPS?
Where the jump address is the 26-bit jump target from the instruction shifted left 2 bits concatenated with the 4 upper bits of the PC (J - Type).
p.18
General Purpose Registers and Memory Addressing
What are the names of the special registers in the MIPS 32 architecture?
$0, $1, $2, ..., $31, Hi, Lo.
p.23
Instruction Encoding Techniques
What is the purpose of the J-Type instruction format?
Used by jump instructions.
p.14
Addressing Modes in Computer Architecture
Name three addressing modes supported by the Intel 80386.
Register, Immediate, Direct.
p.30
Addressing Modes in Computer Architecture
How is the effective 32-bit jump address calculated in MIPS?
PC(31-28), jump_target, 00
p.17
MIPS Architecture Overview
What is the significance of pipelining in MIPS 32 Architecture?
Pipelining allows multiple instruction phases to be processed simultaneously, improving performance.
p.3
Instruction Set Architecture (ISA)
What is the purpose of a compiler in programming?
To translate high-level language programs into machine language.
p.16
General Purpose Registers and Memory Addressing
How do Register-Register architectures compare to Register-Memory architectures?
Register-Register architectures are simpler.
p.8
General Purpose Registers and Memory Addressing
What can a memory address provide access to?
A byte, 2 bytes, 4 bytes, 8 bytes, or more bytes.
p.22
General Purpose Registers and Memory Addressing
What is the role of the $zero register in MIPS?
It always holds the value 0 and cannot be modified.
p.29
Instruction Encoding Techniques
What does the 'rt' field indicate in MIPS Branch I-Type instructions?
It indicates the second register being compared.
p.1
Cost of Software Development
What role do applications play in technology development?
They suggest improvements and provide revenue to fund development.
p.7
General Purpose Registers and Memory Addressing
How do general purpose registers improve performance?
By reducing the need to access slower memory, allowing faster data retrieval and manipulation.
p.4
Computer Architecture Overview
What will be studied in this course?
Both Instruction Set Architecture and Computer Organization.
p.16
General Purpose Registers and Memory Addressing
What is a major reason for using General-Purpose Registers (GPR) architectures?
Registers are faster than memory and reduce memory traffic.
p.16
General Purpose Registers and Memory Addressing
Why are General-Purpose Registers easier for compilers to use?
Because they provide a simpler interface for instruction generation.
p.26
Instruction Encoding Techniques
What does the 'op' field represent in MIPS R-Type instructions?
Opcode, which indicates the basic operation of the instruction.
p.21
General Purpose Registers and Memory Addressing
What is the purpose of the $zero register in MIPS?
It always holds the value 0, forced by hardware.
p.16
Addressing Modes in Computer Architecture
What effect do aligned memory references have on program performance?
Programs with aligned memory references run faster.
p.22
Data Types and Operand Sizes
What is the size of each register in the MIPS architecture?
Each register is 32 bits in size.
p.18
MIPS Architecture Overview
What is the function of the Floating Point Unit (FPU) in MIPS 32?
It handles floating-point arithmetic operations.
p.23
Instruction Encoding Techniques
What are the fields in the R-Type instruction format?
Op, Rs, Rt, Rd, funct, and sa.
p.23
Instruction Encoding Techniques
What are the three instruction formats in a 32-bit instruction set?
Register (R-Type), Immediate (I-Type), and Jump (J-Type).
p.2
Computer Architecture Overview
What does I/O system refer to in computer architecture?
It refers to the input/output system that manages data exchange between the computer and external devices.
p.12
Instruction Encoding Techniques
What is variable encoding in instruction sets?
Instruction length is a variable number of bytes, allowing all addressing modes to be used with all operations.
p.13
Types of Computer Architectures: CISC vs RISC
What does CISC stand for?
Complex Instruction Set Computer.
p.11
Instruction Set Architecture (ISA)
What is a data transfer operation?
Operations that move data between registers, memory, and I/O devices.
p.16
Addressing Modes in Computer Architecture
What do addressing modes specify?
Registers, constants, and memory locations.
p.22
General Purpose Registers and Memory Addressing
What are the two types of registers in the MIPS register file?
General-purpose registers and special-purpose registers.
p.27
Instruction Set Architecture (ISA)
What is the purpose of the 'rs' field in an I-Type ALU instruction?
It is the register source operand.
p.9
Addressing Modes in Computer Architecture
What do addressing modes specify in instructions?
The addresses of their operands.
p.18
Control Signals and Machine Interpretation
What is the purpose of the Integer Multiplier/Divider in MIPS 32?
To perform multiplication and division operations on integers.
p.13
Types of Computer Architectures: CISC vs RISC
How does RISC handle memory operations?
'LOAD' and 'STORE' are independent instructions (register to register).
p.21
General Purpose Registers and Memory Addressing
What does the $ra register store?
The return address used by the jal instruction for function calls.
p.21
General Purpose Registers and Memory Addressing
How can an assembler refer to registers in MIPS?
By name or by number; using names is easier to remember.
p.9
Addressing Modes in Computer Architecture
What does Absolute addressing mode specify?
Accessing a fixed memory address, e.g., LD R1, [1000] means R1 = Mem[1000].
p.24
Addressing Modes in Computer Architecture
How does PC-Relative Addressing work in MIPS?
Where the address is the sum of the PC and the 16-address field in the instruction shifted left 2 bits (I - Type, branches).
p.15
MIPS Architecture Overview
What are the categories of instructions in MIPS 32 Architecture?
Load/Store, Integer Arithmetic, Jump and Branch, Floating Point, Memory Management.
p.18
General Purpose Registers and Memory Addressing
How many general-purpose registers does the MIPS 32 processor have?
32 general-purpose registers.
p.17
MIPS Architecture Overview
What is the role of the instruction set in MIPS 32 Architecture?
It defines the operations that the processor can perform.
p.8
General Purpose Registers and Memory Addressing
What is Little Endian byte ordering?
Memory address X is the address of the least-significant byte (Intel x86).
p.26
Instruction Encoding Techniques
What does 'rd' signify in MIPS R-Type instructions?
The register destination operand.
p.19
MIPS Architecture Overview
What do the special-purpose registers LO and HI hold?
Results of integer multiply and divide.
p.3
MIPS Architecture Overview
What is the purpose of the instruction 'sw $15, 4($2)'?
It stores the value in register $15 into memory at the address in register $2 plus an offset of 4.
p.20
General Purpose Registers and Memory Addressing
What are registers $16 to $23 called in MIPS?
$s0 to $s7, used for saved values.
p.9
Addressing Modes in Computer Architecture
What is the purpose of the Immediate addressing mode?
To use constants directly in operations, e.g., ADD R1, R2, 100 means R1 = R2 + 100.
p.19
MIPS Architecture Overview
How many Floating Point Registers (FPRs) are there in MIPS?
32 Floating Point Registers.
p.13
Types of Computer Architectures: CISC vs RISC
What is the cycle speed and code size characteristic of RISC?
Low cycles per second with large code sizes.
p.19
MIPS Architecture Overview
What is the bit size of Floating Point Registers in MIPS?
They can be either 32-bit or 64-bit.
p.11
Instruction Set Architecture (ISA)
What is an arithmetic operation?
Operations that involve mathematical calculations like addition, subtraction, multiplication, and division.
p.17
MIPS Architecture Overview
How many general-purpose registers does MIPS 32 Architecture have?
32 general-purpose registers.
p.15
MIPS Architecture Overview
How many instruction formats are there in MIPS 32 Architecture?
Three instruction formats.
p.29
Instruction Encoding Techniques
What does the 'op' field represent in MIPS Branch I-Type instructions?
Opcode, operation of the instruction.
p.30
Instruction Set Architecture (ISA)
What are the two types of J-Type instructions in MIPS?
Jump (j) and Jump and Link (jal).
p.2
Computer Architecture Overview
What is the significance of firmware in computer architecture?
Firmware provides low-level control for a device's specific hardware.
p.3
Instruction Encoding Techniques
What does the assembly instruction 'temp = v[k];' represent in machine language?
It corresponds to loading a value from an array into a temporary variable.
p.14
Instruction Encoding Techniques
What is included in the remainder bytes of an instruction?
Address displacement and immediate data.
p.27
Instruction Set Architecture (ISA)
What does the 'op' field represent in an I-Type instruction?
Opcode, operation of the instruction.
p.25
Addressing Modes in Computer Architecture
Name a common addressing mode used in MIPS.
Immediate addressing mode.
p.8
General Purpose Registers and Memory Addressing
In a 32-bit register using Little Endian, how are the bytes ordered?
Byte 0 is at address x, Byte 1 at x+1, Byte 2 at x+2, and Byte 3 at x+3.
p.19
MIPS Architecture Overview
What is the value of Register 0 in MIPS?
Always zero; any value written to R0 is discarded.
p.13
Types of Computer Architectures: CISC vs RISC
How does CISC handle memory operations?
It incorporates 'LOAD' and 'STORE' in instructions (memory-to-memory).
What is the purpose of digital design in computer architecture?
Digital design focuses on the design of circuits and systems that process digital signals.
p.20
General Purpose Registers and Memory Addressing
What are registers $8 to $15 used for in MIPS?
They are called $t0 to $t7 and are used for temporary values.
What is the function of a BIOS?
BIOS (Basic Input/Output System) initializes and tests hardware components during the booting process.
p.29
Instruction Encoding Techniques
How is the offset in MIPS Branch I-Type instructions calculated?
It is equal to the instruction address field multiplied by 4.
p.26
Instruction Encoding Techniques
What is the format of the R-Type instruction fields?
op (6 bits), rs (5 bits), rt (5 bits), rd (5 bits), shamt (5 bits), funct (6 bits).
p.28
Instruction Encoding Techniques
What does the 'address' field represent in MIPS Load/Store I-Type instructions?
A 16-bit memory address offset in bytes added to the base register.
p.26
Instruction Encoding Techniques
What does 'rs' represent in MIPS R-Type instructions?
The first register source operand.
p.15
General Purpose Registers and Memory Addressing
What is the purpose of the PC register in MIPS 32 Architecture?
It holds the address of the next instruction to be executed.
p.2
General Purpose Registers and Memory Addressing
What is Register Transfer Notation (RTN)?
RTN is a method for describing the operations of a computer's registers and data transfer.
p.28
Instruction Encoding Techniques
What does the 'op' field represent in MIPS Load/Store I-Type instructions?
Opcode, which indicates the operation of the instruction.
p.18
MIPS Architecture Overview
What are the components of the MIPS 32 processor's memory unit?
Trap & Memory Unit (Coproc 0) and Floating Point Unit (Coproc 1).
p.25
Instruction Encoding Techniques
What is the purpose of instruction formats in MIPS?
Instruction formats define the layout of bits in an instruction.
p.27
Instruction Set Architecture (ISA)
What does the 'rt' field indicate in an I-Type instruction?
The result destination register.
p.9
Addressing Modes in Computer Architecture
What does the Register addressing mode do?
Adds values in registers, e.g., ADD R1, R2, R3 means R1 = R2 + R3.
p.19
MIPS Architecture Overview
How are double-precision floating-point values stored in MIPS?
Using a pair of registers.
p.18
Control Signals and Machine Interpretation
What is the role of the ALU in the MIPS 32 processor?
It performs arithmetic and logic operations.
p.29
Instruction Encoding Techniques
What is the purpose of the 'rs' field in MIPS Branch I-Type instructions?
It represents the first register being compared.
p.20
General Purpose Registers and Memory Addressing
How many General Purpose Registers (GPRs) are there in MIPS?
32 General Purpose Registers.
p.20
General Purpose Registers and Memory Addressing
What notation does the assembler use to name registers in MIPS?
Dollar notation (e.g., $0, $1, ..., $31).
p.8
General Purpose Registers and Memory Addressing
What is Big Endian byte ordering?
Memory address X is the address of the most-significant byte (SPARC).
What are high-level language programs?
Programs written in a programming language that is more abstract and easier for humans to understand.
p.8
General Purpose Registers and Memory Addressing
In a 32-bit register using Big Endian, how are the bytes ordered?
Byte 0 is at address x+3, Byte 1 at x+2, Byte 2 at x+1, and Byte 3 at x.
p.25
Instruction Encoding Techniques
How many main instruction formats are there in MIPS?
Three main formats: R-type, I-type, and J-type.
p.19
MIPS Architecture Overview
What is the function of the special-purpose program counter (PC)?
It keeps track of the address of the next instruction to be executed.
p.28
Instruction Encoding Techniques
What does the 'rs' field represent in MIPS Load/Store I-Type instructions?
The register containing the memory base address.
p.9
Addressing Modes in Computer Architecture
How does Indexed addressing mode work?
Combines a base address and an index, e.g., LD R1, [R2, R3] means R1 = Mem[R2 + R3].
p.9
Addressing Modes in Computer Architecture
What is the purpose of Scaled Index addressing mode?
To use a scale factor with an index, e.g., LD R1, [R2, R3, s] means R1 = Mem[R2 + R3 << s].
p.9
Addressing Modes in Computer Architecture
What is the function of Post-update addressing mode?
Updates the address after accessing memory, e.g., LD R1, [R2], 8 means R1 = Mem[R2] and R2 = R2 + 8.
p.2
Instruction Set Architecture (ISA)
What is the relationship between compilers and the ISA?
The ISA defines the requirements that compilers must adhere to for effective communication with the CPU.
p.16
Addressing Modes in Computer Architecture
What is the consequence of misalignment in memory references?
It requires multiple aligned memory references.
p.13
Types of Computer Architectures: CISC vs RISC
What is a key characteristic of CISC architecture?
It includes multi-clock complex instructions.
p.25
Addressing Modes in Computer Architecture
What are addressing modes in MIPS?
Addressing modes determine how the operand of an instruction is accessed.
p.26
Instruction Encoding Techniques
What is the function of the 'shamt' field in MIPS R-Type instructions?
It indicates the shift amount used in constant shift operations.
p.26
Instruction Encoding Techniques
What does the 'funct' field do in MIPS R-Type instructions?
It selects the specific variant of operation in the op field.
p.12
Instruction Encoding Techniques
How does instruction encoding impact processor performance?
It affects code size and ease of decoding inside the processor.
p.21
General Purpose Registers and Memory Addressing
What does the $sp register indicate?
The stack pointer, which points to the top of the stack.
p.21
General Purpose Registers and Memory Addressing
What is the role of the $fp register?
It is the frame pointer, which points to the current stack frame.
p.13
Types of Computer Architectures: CISC vs RISC
How do CISC and RISC differ in transistor usage?
CISC uses transistors for storing complex instructions, while RISC spends more transistors on memory registers.
p.11
Instruction Set Architecture (ISA)
What is a control operation?
Operations that manage the flow of execution in a program, such as branching and looping.
p.17
MIPS Architecture Overview
What type of instructions does MIPS 32 Architecture primarily use?
Load/store instructions for data manipulation.
p.25
MIPS Architecture Overview
What is MIPS?
MIPS stands for Microprocessor without Interlocked Pipeline Stages, a type of computer architecture.
p.12
Instruction Encoding Techniques
What is fixed encoding in instruction sets?
All instructions have a single fixed size, typically 32 bits, combining the addressing mode with the opcode.
p.2
Computer Architecture Overview
What does the term 'Software/Hardware Boundary' refer to?
It refers to the interface between software and hardware components in a computer system.
p.17
MIPS Architecture Overview
What is the purpose of the control unit in MIPS 32 Architecture?
To direct the operation of the processor and coordinate the execution of instructions.
p.23
Instruction Encoding Techniques
What fields are present in the I-Type instruction format?
Op, Rs, Rt, and immediate.
p.29
Instruction Encoding Techniques
What is the function of the address field in MIPS Branch I-Type instructions?
It is a branch target offset added to the PC to form the branch address.
p.21
General Purpose Registers and Memory Addressing
What do the $s registers represent in MIPS?
Saved registers that are preserved across function calls.
p.28
Instruction Encoding Techniques
What is the purpose of the 'rt' field in MIPS Load/Store I-Type instructions?
For loads, it is the destination register; for stores, it is the source register of the value to be stored.
p.25
Instruction Encoding Techniques
What does J-type instruction format represent?
It is used for jump instructions.
p.20
General Purpose Registers and Memory Addressing
What does register $ra represent in MIPS?
It is the return address register.
p.27
Addressing Modes in Computer Architecture
What type of addressing mode is used in I-Type instructions?
Immediate Addressing (Mode 2).
p.13
Types of Computer Architectures: CISC vs RISC
What does RISC stand for?
Reduced Instruction Set Computer.
p.18
MIPS Architecture Overview
What does the Execution & Integer Unit in MIPS 32 do?
It executes integer operations and manages the main processing.
p.3
Instruction Encoding Techniques
What is the significance of the binary instruction '1000110001100010000000000000000'?
It represents a specific machine language instruction in binary format.
p.12
Instruction Encoding Techniques
What is hybrid encoding in instruction sets?
It features few instruction lengths to reduce variability and includes compressed encoding of frequently used instructions.
p.20
General Purpose Registers and Memory Addressing
What is special about register $0 in MIPS?
Register $0 is always zero; any value written to it is discarded.
p.3
MIPS Architecture Overview
What does the instruction 'v[k] = v[k + 1];' do in assembly language?
It assigns the value of the next element in the array to the current element.
p.27
Instruction Set Architecture (ISA)
What does the 'immediate' field represent in an I-Type ALU instruction?
Constant second operand for ALU instruction.
p.25
Instruction Encoding Techniques
What is the I-type instruction format used for?
It is used for immediate values and memory access.
p.9
Addressing Modes in Computer Architecture
What is the function of Displacement addressing mode?
Accessing memory with an offset, e.g., LD R1, [R2, 8] means R1 = Mem[R2 + 8].
p.9
Addressing Modes in Computer Architecture
What does Pre-update addressing mode do?
Updates the address before accessing memory, e.g., LD R1, [R2, 8]! means R2 = R2 + 8 and R1 = Mem[R2].
p.12
Instruction Encoding Techniques
Which architectures use fixed encoding?
MIPS, ARM, Power, SPARC, etc.
p.22
General Purpose Registers and Memory Addressing
Which registers are used for function return values in MIPS?
The $v0 and $v1 registers.
p.13
Types of Computer Architectures: CISC vs RISC
What is a defining feature of RISC architecture?
It utilizes a small, highly-optimized set of instructions.
p.22
General Purpose Registers and Memory Addressing
What is the function of the $sp register in MIPS?
It serves as the stack pointer.
p.9
Addressing Modes in Computer Architecture
What are the possible locations for operands?
Registers, constants, or in memory.
p.26
Instruction Encoding Techniques
What type of instructions does R-Type encompass in MIPS?
All ALU instructions that use three registers.
p.13
Types of Computer Architectures: CISC vs RISC
What is the cycle speed and code size characteristic of CISC?
Small code sizes with high cycles per second.
p.20
General Purpose Registers and Memory Addressing
What is the purpose of defining names for all registers in MIPS?
To standardize their use in programs.
p.9
Addressing Modes in Computer Architecture
What does Register Indirect addressing mode involve?
Using the address contained in a register, e.g., LD R1, [R2] means R1 = Mem[R2].
p.28
Addressing Modes in Computer Architecture
What addressing mode is used in MIPS Load/Store I-Type instructions?
Base or Displacement Addressing (Mode 3).
What is VLSI placement and routing?
VLSI placement and routing involve arranging and connecting components on a chip to optimize performance.
p.10
Data Types and Operand Sizes
What do 64-bit architectures support?
64-bit operands and memory addresses.
