What is the purpose of the program counter (PC) in a datapath?
To read the address of the instruction and increment it.
What are the two main components needed to implement R-format ALU operations?
The register file and the ALU.
How many read ports and write ports does the register file have?
Two read ports and one write port.
What must be asserted to perform a register write?
The write control signal.
p.19
Single-Cycle Implementation
Why is a single-cycle implementation not used in modern designs?
It is inefficient due to the long clock cycle required for the longest instruction path.
p.5
Control Signals in Datapath
What does the control unit in a datapath do?
It generates a write signal for each state element, selector control for each multiplexor, and the ALU control.
p.19
Single-Cycle Implementation
What determines the clock cycle length in a single-cycle design?
The longest possible path in the processor, typically a load instruction.
p.11
Control Signals in Datapath
How many control lines are required for the multiplexors in the datapath?
Seven single-bit control lines plus a 2-bit ALUOp control signal.
p.11
Single-Cycle Implementation
What additional components are added to the simple datapath?
Instruction labels and an extra multiplexor for the Write register number input.
How does pipelining improve efficiency in processors?
By executing multiple instructions simultaneously.
What is the first step in executing a load word instruction?
An instruction is fetched from the instruction memory, and the PC is incremented.
p.20
Single-Cycle Implementation
What is a limitation of single-cycle implementation in processors?
It doesn't work well for complex instruction sets or floating-point units due to the clock cycle being equal to the worst-case delay for all instructions.
p.11
Control Signals in Datapath
What is the exception for setting control signals during instruction execution?
The PCSrc control line, which is asserted for branch on equal instructions.
What additional component is needed for branch instructions in the datapath?
An additional multiplexor to select between the sequentially following instruction address (PC + 4) or the branch target address.
p.3
Control Signals in Datapath
What does the Zero signal from the ALU indicate?
It indicates whether the result of an operation is 0.
How is the jump instruction implemented in the datapath?
By replacing the lower 28 bits of the PC with the lower 26 bits of the instruction shifted left by 2 bits.
p.19
Control Signals in Datapath
What additional component is used to handle jump instructions in the datapath?
An additional multiplexor.
p.4
Control Signals in Datapath
How can multiple instruction classes share a datapath element?
By using a multiplexor and control signal to select among multiple inputs.
What happens when the Branch control signal is 0?
The PC is unconditionally replaced with PC + 4.
p.15
Memory Access Instructions
What happens to the data memory value in a store instruction?
It is written to memory instead of being written to the register file.
p.4
Control Signals in Datapath
What does the control logic decide in the branch datapath?
Whether to replace the PC with the incremented PC or the branch target based on the Zero output of the ALU.
What happens to the 16-bit address field in branch equal instructions?
It is sign-extended, shifted, and added to the PC + 4 to compute the branch target address.
What happens when the branch condition is true?
The branch target address becomes the new PC, and the branch is taken.
What components are involved in computing the branch target address?
A sign extension unit and an adder.
What is the main difference between arithmetic-logical instructions and memory instructions in a datapath?
Arithmetic-logical instructions use the ALU with inputs from two registers, while memory instructions can also use the ALU for address calculation with a sign-extended 16-bit offset.
p.9
Control Signals in Datapath
Why are don’t-care terms included in the truth table?
To indicate that the output does not depend on the value of certain inputs, allowing for a more compact representation.
Which fields specify the registers to be read for R-type instructions?
The rs and rt fields, located at positions 25:21 and 20:16.
p.3
Memory Access Instructions
What does the sign extension unit do?
It sign-extends a 16-bit input into a 32-bit output.
p.8
Control Signals in Datapath
What is the significance of using multiple levels of decoding in control units?
It can reduce the size of the main control unit and potentially increase the speed of the control unit.
What is the significance of edge-triggered writes in the register file?
They allow reading and writing the same register within a clock cycle.
How is the destination register specified for load and R-type instructions?
For load, it is in bit positions 20:16 (rt); for R-type, it is in bit positions 15:11 (rd).
What analogy is used to explain pipelining?
The laundry process, comparing non-pipelined and pipelined approaches.
p.11
Control Signals in Datapath
What does the ALUOp control signal do?
It determines the operation of the ALU based on the opcode field of the instruction.
p.4
Single-Cycle Implementation
Why must some datapath resources be duplicated?
Because no resource can be used more than once per instruction.
p.14
Control Signals in Datapath
What determines the setting of the control lines in the processor?
The opcode fields of the instruction.
p.7
Control Signals in Datapath
What should MemtoReg be set to in a simple implementation scheme?
To cause the correct register destination to be sent to the register file.
How is the ALU operation controlled?
Using a 4-bit ALU operation signal.
p.18
Single-Cycle Implementation
What is the purpose of extending the datapath and control in the MIPS architecture?
To include the jump instruction in the instruction set.
p.10
Memory Access Instructions
In load and store instructions, where is the base register located?
In bit positions 25:21 (rs).
What is the function of the 'Shift left 2' unit in the branch datapath?
To add two zeros to the low-order end of the sign-extended offset field.
What does the RegWrite signal indicate for R-type instructions?
It indicates that a register is being written (RegWrite = 1).
p.18
Control Signals in Datapath
What additional control signal is needed for the jump instruction?
The Jump control signal, asserted when the opcode is 2.
p.17
Control Signals in Datapath
Which opcode corresponds to the R-format instruction?
Op5 and Op2 are used to detect an R-format instruction.
p.17
Control Signals in Datapath
What does the ALUSrc signal indicate for different opcodes?
ALUSrc is 0 for R-format, and 1 for lw and sw.
What is required to build a datapath that handles both memory-reference and arithmetic-logical instructions?
A single register file, a single ALU, and necessary multiplexors to support different sources for the second ALU input and data stored into the register file.
p.19
Single-Cycle Implementation
How many functional units are used in series for a load instruction?
Five functional units: instruction memory, register file, ALU, data memory, and register file.
p.11
Control Signals in Datapath
What is the role of the control unit in setting control signals?
It sets all control signals based on the opcode field, except for the PCSrc signal.
p.4
Single-Cycle Implementation
What is required for instruction memory in a single datapath?
A separate memory for instructions and data.
p.11
Control Signals in Datapath
What does the branch control logic determine?
Whether the PC is written with the incremented PC or the branch target address.
What is the purpose of the shamt field in R-type instructions?
It is used only for shift operations.
p.7
Single-Cycle Implementation
What is one reason for having separate memories in the single-cycle datapath?
Having separate memories is less expensive.
p.10
Memory Access Instructions
What is the opcode for load and store instructions?
Load has an opcode of 35 and store has an opcode of 43.
How is the ALUOp field set for branch instructions?
It is set for a subtract operation (ALU control = 01) to test for equality.
p.14
Control Signals in Datapath
What does the 'X' signify in the control signal settings for lw and sw?
It indicates a don't care condition.
p.13
Control Signals in Datapath
What is the significance of the PCSrc signal in the simple implementation scheme?
It is a derived signal used to control the selection of the next PC, rather than coming directly from the control unit.
p.12
Control Signals in Datapath
How does the control unit determine the setting of control signals?
Based on the opcode bits 31 to 26.
p.9
Control Signals in Datapath
What does the truth table for the 4-bit ALU control show?
It shows how the ALU control is set depending on the ALUOp and function code inputs.
What is the purpose of bits 15:11 in the instruction?
To select the destination register for the ALU result.
What does the ALU compute in relation to the register file and instruction?
The sum of the value read from the register file and the sign-extended lower 16 bits of the instruction (offset).
p.9
Control Signals in Datapath
What is the purpose of identifying the fields of an instruction in the design process?
To understand how to connect the fields of an instruction to the datapath.
How does the branch-on-equal instruction operate?
It operates like an R-format instruction, using the ALU output to determine whether the PC is written with PC + 4 or the branch target address.
From where do the upper 4 bits of the jump address come?
From the PC of the jump instruction plus 4.
What is the purpose of the multiplexors in the datapath?
To select between different data sources for processing.
p.17
Control Signals in Datapath
What is the input for the control function in the implementation?
The 6-bit opcode field, Op [5:0].
p.17
Control Signals in Datapath
What does the truth table in Figure 4.22 specify?
It completely specifies the control function for the simple single-cycle implementation.
How is the next PC selected in the simple implementation scheme?
Using an AND gate that combines the branch control signal and the Zero output from the ALU.
p.6
Control Signals in Datapath
What does the 'Sign-extend' operation do in the datapath?
It extends a 16-bit instruction to 32 bits.
p.12
Control Signals in Datapath
What is the significance of the clock in state elements?
The clock is used in controlling writes, and gating it externally can create timing problems.
p.11
Control Signals in Datapath
How is the PCSrc signal generated?
By ANDing the Branch signal from the control unit with the Zero signal from the ALU.
p.5
Memory Access Instructions
What should MemtoReg be set to for a load instruction?
It should be set to cause the data from memory to be sent to the register file.
Where is the opcode field located in the instruction format?
In bits 31:26, referred to as Op[5:0].
p.8
Control Signals in Datapath
What does the ALUOp control field indicate?
The operation to be performed: add (00), subtract (01), or determined by the funct field (10).
p.8
Control Signals in Datapath
How is the 4-bit ALU control input generated?
Using a small control unit that takes the function field of the instruction and the ALUOp control field as inputs.
p.3
Memory Access Instructions
What is the significance of the read signal in the memory unit?
It is necessary because reading from an invalid address can cause problems.
How is the branch target address calculated?
PC + 4 is added to the sign-extended, lower 16 bits of the instruction (offset) shifted left by two.
What does the ALU use to generate the ALU function?
The function code (bits 5:0, which is the funct field, of the instruction).
p.12
Control Signals in Datapath
What does the ALUSrc signal control?
The second ALU operand comes from the sign-extended, lower 16 bits of the instruction.
What is the significance of shifting the offset field left by 2 bits?
It converts the offset into a word offset, increasing its effective range by a factor of 4.
What is the main advantage of the pipelined approach to laundry?
It takes much less time by overlapping tasks.
p.19
Single-Cycle Implementation
What is a significant penalty of using a single-cycle design?
The clock cycle is too long, leading to poor overall performance.
What is a delayed branch in the MIPS instruction set?
An instruction where the one immediately following the branch is always executed, regardless of the branch condition.
p.9
Control Signals in Datapath
What is the process after constructing the truth table?
The truth table can be optimized and then turned into gates.
p.16
Memory Access Instructions
How is the sum from the ALU used in the datapath?
As the address for the data memory.
How does the jump instruction compute the target PC?
It computes the target PC differently than a branch instruction and is not conditional.
p.9
Control Signals in Datapath
What does the truth table entry with ALUOp 1 and function code X indicate?
It indicates that the ALU control can be set to different values based on the function code.
p.2
Memory Access Instructions
What does the store word instruction do?
Stores the value from register $t1 into memory at the address computed from $t2 and the offset.
p.13
Control Signals in Datapath
What is the role of the control unit in the simple implementation scheme?
It computes the setting of the control lines and generates control signals for various operations.
p.13
Control Signals in Datapath
What are the outputs of the control unit?
Signals for multiplexors (RegDst, ALUSrc, MemtoReg), control signals for register file and data memory (RegWrite, MemRead, MemWrite), a branch control signal, and a 2-bit ALU control signal (ALUOp).
p.17
Control Signals in Datapath
What is the output for the RegWrite signal in the truth table?
RegWrite is asserted for two different combinations of the inputs.
What is the function of the 'Zero' signal in the datapath?
It indicates whether the ALU result is zero.
p.4
Single-Cycle Implementation
What is the purpose of combining datapath components into a single datapath?
To execute all instructions in one clock cycle.
What are the three instruction classes mentioned?
R-type, branch, and load-store instructions.
p.19
Control Signals in Datapath
How is the jump target address calculated?
By shifting the lower 26 bits of the jump instruction left 2 bits and concatenating with the upper 4 bits of PC + 4.
p.13
Single-Cycle Implementation
What is the first step in executing an instruction in a simple implementation scheme?
The instruction is fetched, and the PC is incremented.
p.7
Single-Cycle Implementation
Which instructions are covered in the simple implementation of the MIPS subset?
Load word (lw), store word (sw), branch equal (beq), and arithmetic-logical instructions (add, sub, AND, OR, set on less than).
p.17
Control Signals in Datapath
What does the Zero result from the ALU determine?
It is used to decide which adder result to store into the PC.
p.16
Control Signals in Datapath
What is the purpose of the control lines in the datapath?
To activate the appropriate datapath units and connections during instruction execution.
p.12
Control Signals in Datapath
What happens when the PCSrc signal is asserted?
The PC is replaced by the output of the adder that computes the branch target.
p.6
Memory Access Instructions
What does 'MemRead' and 'MemWrite' control in the datapath?
They control reading from and writing to memory.
What does the term 'pipelining' refer to in computer architecture?
An implementation technique in which multiple instructions are overlapped in execution, similar to an assembly line.
p.9
Control Signals in Datapath
What is the significance of the ALUOp bits being set to 00 in the truth table?
When ALUOp bits are 00, the ALU control is always set to 0010, regardless of the function code.
p.14
Control Signals in Datapath
What is the ALUOp field set to for R-type instructions?
10, indicating that the ALU control should be generated from the funct field.
p.7
Single-Cycle Implementation
Why must the single-cycle datapath have separate instruction and data memories?
Because the formats of data and instructions are different in MIPS, and hence different memories are needed.
p.3
Memory Access Instructions
What is the function of the memory unit in the datapath?
It serves as a state element with inputs for address and write data, and an output for the read result.
How does pipelining affect branches in the MIPS architecture?
It leads to the implementation of delayed branches to manage instruction execution order.
p.12
Control Signals in Datapath
What happens when the RegDst signal is asserted?
The register destination number for the Write register comes from the rd field (bits 15:11).
p.2
Memory Access Instructions
What is required to compute the memory address for load and store instructions?
The base register $t2 and the 16-bit signed offset field.
p.8
Control Signals in Datapath
When does the funct field influence the ALU control input?
When the ALUOp value is 10.
p.12
Control Signals in Datapath
What occurs when the MemWrite signal is asserted?
Data memory contents designated by the address input are replaced by the value on the Write data input.
p.15
Memory Access Instructions
What is the main difference between a load instruction and a store instruction?
The memory control indicates a write for store, while it indicates a read for load.
What does the ALU result represent in the context of a load instruction?
The address from which data will be read from memory.
p.9
Control Signals in Datapath
What is a don’t-care term in logic?
An element of a logical function where the output does not depend on the values of all the inputs.
p.17
Single-Cycle Implementation
What is the first step in the simple implementation scheme?
Two registers, $t1 and $t2, are read from the register file.
p.14
Memory Access Instructions
What is the purpose of the ALUSrc field in load (lw) and store (sw) instructions?
To perform the address calculation.
p.7
Single-Cycle Implementation
Why can't a single-ported memory be used in a single-cycle datapath?
Because the processor operates in one cycle and cannot use it for two different accesses within that cycle.
p.14
Memory Access Instructions
What is the significance of the MemtoReg field when RegWrite is 0?
It is irrelevant since the register is not being written.
p.16
Control Signals in Datapath
What does the Zero output from the ALU determine?
It is used to select the next program counter from between two candidates.
What is the instruction format for the jump instruction?
Field 000010, with bit positions 31:26 for opcode and 25:0 for address.
p.18
Control Signals in Datapath
What does the additional multiplexor do in the jump instruction implementation?
It selects the source for the new PC value, either the incremented PC, branch target PC, or jump target PC.
p.12
Control Signals in Datapath
What is the effect of asserting the MemRead signal?
Data memory contents designated by the address input are put on the Read data output.
p.12
Control Signals in Datapath
What does the MemtoReg signal determine?
The value fed to the register Write data input comes from the data memory.
p.3
Memory Access Instructions
What are the two units needed to implement loads and stores in the datapath?
The data memory unit and the sign extension unit.
p.15
Control Signals in Datapath
What control signals are asserted during the execution of a load instruction?
MemRead, RegWrite, and others related to the datapath.
What operation does the ALU perform on the data values read from the register file?
The ALU performs a subtract.
p.12
Control Signals in Datapath
What is the effect of asserting the RegWrite signal?
The register on the Write register input is written with the value on the Write data input.
What function does the ALU perform for load word and store word instructions?
It computes the memory address by addition.
What determines the ALU's action for R-type instructions?
The value of the 6-bit funct (function) field.
How is the branch target address calculated in the beq instruction?
By adding the sign-extended offset field to the PC (Program Counter).
What is the effect of a branch not taken?
The PC becomes the address of the instruction that follows the branch.
Where is the data from the memory unit written?
Into the register file, with the register destination given by bits 20:16 of the instruction.
p.2
Memory Access Instructions
What is the general form of the MIPS load word instruction?
lw $t1, offset_value($t2)
What is the first step in the execution of an instruction?
An instruction is fetched from the instruction memory, and the PC is incremented.
What types of instructions can the simple datapath for the core MIPS architecture execute?
Load-store word, ALU operations, and branches.
What is the purpose of the beq instruction?
To compare two registers and branch to a target address if they are equal.
p.18
Single-Cycle Implementation
What is a single-cycle implementation?
An implementation where an instruction is executed in one clock cycle.
How many additional multiplexors are needed to integrate branches into the simple datapath?
One additional multiplexor.
What is the significance of the ALU in the datapath?
It performs arithmetic and logical operations.
What is the role of the 'PC' in the datapath?
It holds the address of the next instruction to be executed.
p.12
Control Signals in Datapath
What is the purpose of the multiplexor in the control signals?
It selects the input corresponding to the asserted control signal.
